Photolithography is an important process for pattern transferring during manufacturing an integrated circuit. Therefore, the precision level of pattern stacks between layers nearly all depends on the alignment capability of the photolithographic process. Due to the limitations of the precision level of an alignment mechanism and characteristics of photoresist materials, however, there is more or less possibility that misalignment may occur. Thus, one target of industrial practices is to find a way to best-determine whether the misalignment occurs during manufacturing semiconductor components.
The test methods to determine whether the misalignment between layers occurs in the components generally include using optical examination systems, e.g. scanning electron microscope (SEM), and test structures disposed on the chips. Determining the misalignment by an optical examination system, however, requires more time and efforts, and usually does not result in enough precision due to native limitation of instrument resolution. Therefore, techniques of on-chip test structures come with the tide of fashion.
While size of the semiconductor components becomes smaller and smaller, however, the misalignment during a photolithographic process becomes more and more difficult to be verified. Due to the component size reduction, the test structure needs to not only determine whether the misalignment occurs but also quantify an offset amount and detect the direction of the misalignment for future references. Moreover, as achieving the purpose of quantifying test results, the test structure must be compatible with the current manufacturing process to monitor the process instantaneously.
To solve the problems described above, a desirable design of the test structure is needed to quantify the misalignment during the semiconductor manufacturing process.